1. Field of the Invention
The present invention relates to a semiconductor memory device, and, more specifically, to an electrically rewritable nonvolatile semiconductor memory integrated circuit (electrically erasable programmable read only memory) (hereinafter, referred to as EEPROM). The invention also relates to a semiconductor memory device including a circuit having a test operation mode different from a general operation mode, which can switch an operation mode to the test operation mode by applying to a predetermined external terminal a voltage not smaller than a recommended voltage for the general operation mode.
2. Description of the Related Art
A conventional semiconductor memory device has a function of switching to the a test operation mode by applying a high voltage to an external terminal. The high voltage used herein means a voltage beyond a range of a power source voltage applied in the general operation mode. For example, if a maximum operation power source voltage of an integrated circuit (IC) is 5 V, the voltage higher than 5 V corresponds to the “high voltage”. For example, a high voltage of about 10 V is generally applied.
To realize the above function, a voltage detection circuit for detecting the high voltage is incorporated. In the foregoing example, a detection voltage of the voltage detection circuit is set to more than 5 V and less than 10 V (in general, 9 V) and thus, the voltage of 10 V is applied to the predetermined external terminal. As a result, the voltage detection circuit outputs a detection signal to switch the operation mode to the test operation mode. The detection voltage is determined according to a specification regarding the maximum operation power source voltage and device characteristics of a semiconductor process used. Thus, it is conceivable to adopt a voltage condition other than that of the above example.
The external terminal applied with the high voltage is a terminal exclusively dedicated to detection of the test operation mode without having other functions. Also, the external terminal is a power source voltage application terminal and may double as a terminal for the power source voltage application and a terminal having the function of detecting the voltage for switching the mode to the test operation mode. Also, the external terminal serves as an input terminal, an output terminal, or an input/output terminal and may have both of a function specific to the corresponding terminal and the function of detecting the voltage for switching the mode to the test operation mode (e.g., refer to JP 2002-15599 A (pp. 2–4, FIG. 1)).
A conventional voltage detection circuit for detecting the test operation mode involves the following problem. FIG. 2 is a block diagram showing an external terminal 21 having a function of detecting a test operation mode, a voltage detection circuit 23 for detecting a test operation mode, and a protective transistor 22 for protecting the IC when being subjected to an electrostatic noise.
FIG. 3 is a circuit diagram showing a conventional voltage detection circuit. The circuit is constituted of a pad 31 to which a high voltage is applied for switching the mode to the test operation mode, an n number of NMOS transistors 32, a resistor 33, and an inverter 34. The NMOS transistors 32 and the resistor 33 are connected in series between the pad 31 and the ground voltage. A high voltage side of the resistor 3 serves as an input terminal of the inverter 34. In this circuit, when the pad 31 is applied with the voltage higher than a total value (n×Vth) of threshold voltages of the NMOS transistors 32 connected in series in n stages, an output level of the inverter 34 is inverted from an H level to an L level, thereby switching the mode to the test operation mode.
The protective transistor 22 shown in FIG. 2 is generally an NMOS transistor and also an off-transistor where a gate voltage and a source voltage are connected to the ground and a drain voltage is connected to the pad. As a MOS structure of the protective transistor, the transistor of the MOS structure showing a lower drain breakdown voltage of the off-transistor than the NMOS transistor used in the voltage detection circuit is used. Thus, the protective transistor undergoes the breakdown ahead of an internal transistor to be protected to achieve a function of protecting an internal circuit.
The drain voltage of the protective transistor is also connected to the drain of the NMOS transistor, which is connected to the pad of the voltage detection circuit as mentioned above.
Accordingly, the detection voltage of the voltage detection circuit should be set lower than the drain breakdown voltage of the protective transistor. Assuming that the detection voltage is set higher than the drain breakdown voltage of the protective transistor, even if the voltage not smaller than the breakdown voltage is applied, the protective transistor causes the breakdown and the voltage not smaller than the breakdown voltage is not applied. As a result, the voltage detection circuit cannot detect the objective voltage, which specifically means that the mode cannot be switched to the test operation mode.
FIG. 4 is a graph showing a relationship between the voltage applied to the pad and a current flowing through the NMOS transistors connected in series in the voltage detection circuit.
When the voltage applied to the pad increases, the current corresponding to the applied voltage is caused to flow into the voltage detection circuit. If the detection voltage (n×Vth) is applied thereto, the mode is switched to the test operation mode as mentioned above. With the applied voltage lower than the detection voltage, the current less than the detection current flows into the voltage detection circuit.
In the power source voltage range of the general operation mode, the current leads to a leak current at the terminal; in general, the leak current needs to be set to a constant current value or smaller from the viewpoint of IC specification of the EEPROM. In particular, the leak current increases during a low-temperature operation and thus, the leak current in the power source voltage range in the general operation mode determines a product quality as an important factor.
Further, if the detection voltage is increased, the leak current at the maximum operation voltage lessens, whereas if the detection voltage is decreased, the leak current at the maximum operation voltage increases. In other words, to suppress the leak current, the detection voltage should be set as high as possible.
A permissible upper limit set in the detection voltage circuit is restricted according to the drain breakdown voltage of the protective off-transistor and hence, the drain breakdown voltage needs to be set high.
However, the drain breakdown voltage is determined according to a design rule of the semiconductor process inclusive of a gate oxide film thickness of the MOS transistor, a diffusion region concentration of the drain, a concentration of a field region, or the like. Therefore, it is impossible to increase the drain breakdown voltage alone without a careful consideration in the case of following up the preset semiconductor process.
The problem about the increased leak current is mostly conspicuous in the IC with a wide operation temperature range, which is particularly capable of operating at a low temperature.
Also, in many cases, the above problem is conspicuous in the IC having the wide power source voltage range in the general operation mode, in particular, the high maximum operation voltage.
Further, the above problem is particularly conspicuous when the drain breakdown voltage of the off-transistor used as the protective transistor is low in many cases.
In addition, the above problem is often conspicuous particularly when a subthreshold current amount of the NMOS transistor constituting the voltage detection circuit is large.